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6A595
ADVANCE INFORMATION
(Subject to change without notice) March 22, 2000
8-BIT SERIAL-INPUT, DMOS POWER DRIVER
The A6A595KA and A6A595KLB combine an 8-bit CMOS shift register and accompanying data latches, control circuitry, and DMOS power driver outputs. Power driver applications include relays, solenoids, and other medium-current or high-voltage peripheral power loads. The serial-data input, CMOS shift register and latches allow direct interfacing with microprocessor-based systems. Serial-data input rates are over 5 MHz. Use with TTL may require appropriate pull-up resistors to ensure an input logic high. A CMOS serial-data output enables cascade connections in applications requiring additional drive lines. The A6A595 DMOS open-drain outputs are capable of sinking up to 500 mA. All of the output drivers are disabled (the DMOS sink drivers turned off) by the OUTPUT ENABLE input high. The A6A595KA is furnished in a 20-pin dual in-line plastic package. The A6A595KLB is furnished in a 24-lead wide-body, smalloutline plastic batwing package (SOIC) with gull-wing leads. Copper lead frames, reduced supply current requirements, and low on-state resistance allow both devices to sink 150 mA from all outputs continuously, to ambient temperatures over 85C.
Data Sheet 26185.121
A6A595KA (DIP)
OUT2 OUT3 REGISTER CLEAR OUTPUT ENABLE POWER GROUND POWER GROUND STROBE CLOCK OUT4 OUT5 1 2 LATCHES 3 4 5 6 7 8 9 10 ST CLK REGISTER LATCHES 12 11 CLR OE REGISTER VDD 18 17 16 15 14 13 20 19 OUT1 OUT0 SERIAL DATA IN LOGIC SUPPLY POWER GROUND POWER GROUND LOGIC GROUND SERIAL DATA OUT OUT7 OUT6
Dwg. PP-029-15
ABSOLUTE MAXIMUM RATINGS
at TA = 25C
Output Voltage, VO ............................... 50 V Output Drain Current, Continuous, IO .......................... 350 mA* Peak, IOM ................................. 1100 mA Single-Pulse Avalanche Energy, EAS ................................................. 75 mJ Logic Supply Voltage, VDD .................. 7.0 V Input Voltage Range, VI ................................... -0.3 V to +7.0 V Package Power Dissipation, PD ........................................... See Graph Operating Temperature Range, TA ................................. -40C to +125C Storage Temperature Range, TS ................................. -55C to +150C
* Each output, all outputs on. Pulse duration 100 s, duty cycle 2%. Caution: These CMOS devices have input static protection (Class 3) but are still susceptible to damage if exposed to extremely high static electrical charges.
FEATURES
I 50 V Minimum Output Clamp Voltage I 350 mA Output Current (all outputs simultaneously) I 1 Typical rDS(on) I Internal Short-Circuit Protection I Low Power Consumption I Replacements for TPIC6A595N and TPIC6A595DW
Always order by complete part number: Part Number Package RJA A6A595KA 20-pin DIP 55C/W A6A595KLB 24-lead SOIC 55C/W
RJC 25C/W --
RJT -- 6C/W
6A595 8-BIT SERIAL-INPUT, DMOS POWER DRIVER
A6A595KLB (SOIC)
5
SUFFIX 'LB', R JT = 6.0C/W
1 2 LATCHES REGISTER CLEAR OUTPUT ENABLE 3 4 5 6 7 8 9 10 11 12 ST CLK REGISTER OUT4 LATCHES 14 13 CLR OE REGISTER VDD 22 21 20 19 18 17 16 15 SERIAL DATA IN LOGIC SUPPLY POWER GROUND POWER GROUND POWER GROUND POWER GROUND LOGIC GROUND SERIAL DATA OUT OUT7 OUT6 24 23
ALLOWABLE PACKAGE POWER DISSIPATION IN WATTS
OUT2 OUT3
OUT1 OUT0
4
3
SUFFIX 'A', R JC = 25C/W
POWER GROUND POWER GROUND POWER GROUND POWER GROUND STROBE
2
1
R JA = 55C/W
CLOCK
0 25 50 75 100 TEMPERATURE IN C 125 150
Dwg. GP-049-5
OUT5
Dwg. PP-029-16A
FUNCTIONAL BLOCK DIAGRAM
REGISTER CLEAR
(ACTIVE LOW)
CLOCK SERIAL DATA IN STROBE OUTPUT ENABLE
(ACTIVE LOW)
V DD
LOGIC SUPPLY SERIAL DATA OUT
SERIAL-PARALLEL SHIFT REGISTER
D-TYPE LATCHES
LOGIC GROUND
SUB
CURRENT LIMIT AND CHARGE PUMP
POWER GROUND
POWER GROUND
OUT 0
OUT N
Dwg. FP-013-6
Power grounds must be connected together externally.
115 Northeast Cutoff, Box 15036 Worcester, Massachusetts 01615-0036 (508) 853-5000 Copyright (c) 2000, Allegro MicroSystems, Inc.
6A595 8-BIT SERIAL-INPUT, DMOS POWER DRIVER
V
DD
OUT
IN
Dwg. EP-063-5
DMOS POWER DRIVER OUTPUT
Dwg. EP-010-10
VDD
LOGIC INPUTS
RECOMMENDED OPERATING CONDITIONS
over operating temperature range Logic Supply Voltage Range, VDD ............... 4.5 V to 5.5 V High-Level Input Voltage, VIH ............................ 0.85VDD Low-level input voltage, VIL ................................. 0.15VDD
OUT
Dwg. EP-063-4
SERIAL DATA OUT TRUTH TABLE
Shift Register Contents Data Clock Input Input H L X I0 H L I1 I2 ... ... ... ... ... ... I6 I7 Serial Data Output Strobe R6 R6 R7 X P7 -- R0 R1 R2 P0 P1 P2 X L = Low Logic Level H = High Logic Level X = Irrelevant X X ... ... ... R6 R7 P6 P7 X X L H P0 P1 P2 H H H ... ... P6 P7 H H Latch Contents I0 I1 I2 ... I6 I7 Output Enable I0 Output Contents I1 I2 ... I6 I7
R0 R1 R0 R1
R5 R6 R5 R6 R6 R7 X X
R0 R1 R2 X X X
P0 P1 P2
P6 P7
P = Present State
R = Previous State
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6A595 8-BIT SERIAL-INPUT, DMOS POWER DRIVER
ELECTRICAL CHARACTERISTICS at TA = +25C, VDD = 5 V, tir = tif 10 ns (unless otherwise specified).
Limits Characteristic Output Breakdown Voltage Off-State Output Current Static Drain-Source On-State Resistance Source-to-Drain Diode Voltage Nominal Output Current Output Current Logic Input Current Symbol V(BR)DSX IDSX Test Conditions IO = 1 mA VO = 40 V VO = 40 V, TA = 125C Min. 50 -- -- -- -- -- -- 0.6 -- -- 4.9 4.5 -- -- -- -- -- -- -- -- Typ. -- 0.1 0.2 1.0 1.7 1.0 350 0.8 -- -- 4.99 4.7 0 0.3 100 60 55 40 0.5 -- Max. -- 1.0 5.0 1.5 2.5 -- -- 1.1 1.0 -1.0 -- -- 0.1 0.5 -- -- -- -- 5.0 1.3 Units V A A V mA A A A V V V V ns ns ns ns mA mA
rDS(on)
IO = 350 mA IO = 350 mA, TA = 125C
VSD IO(nom) IO(chop) IIH IIL
IF = 350 mA VDS(on) = 0.5 V, TA = 85C IO at which chopping starts, TC = 25C VI = VDD VI = 0 IOH = -20 A IOH = -4 mA
SERIAL-DATA Output Voltage
VOH
VOL
IOL = 20 A IOL = 4 mA
Prop. Delay Time
tPLH tPHL
IO = 350 mA, CL = 30 pF IO = 350 mA, CL = 30 pF IO = 350 mA, CL = 30 pF IO = 350 mA, CL = 30 pF Outputs OFF fclk = 5 MHz, CL = 30 pF, Outputs OFF
Output Rise Time Output Fall Time Supply Current
tr tf IDD(off) IDD(fclk)
Typical Data is at VDD = 5 V and is for design information only. NOTE -- Pulse test, duration 100 s, duty cycle 2%.
115 Northeast Cutoff, Box 15036 Worcester, Massachusetts 01615-0036 (508) 853-5000
6A595 8-BIT SERIAL-INPUT, DMOS POWER DRIVER
TIMING REQUIREMENTS and SPECIFICATIONS
(Logic Levels are VDD and Ground)
C CLOCK A SERIAL DATA IN DATA tp SERIAL DATA OUT D STROBE
50% 50% 50%
LOGIC SYMBOL
B
50%
OUTPUT ENABLE STROBE REGISTER CLEAR CLOCK
G3 C2 R SRG8 C1 1D 2 OUT0 OUT1 OUT2 OUT3
DATA E
SERIAL DATA IN
OUTPUT ENABLE
LOW = ALL OUTPUTS ENABLED
OUT4
tp OUT N
HIGH = OUTPUT OFF
50%
OUT5 OUT6 2 OUT7 SERIAL DATA OUT Dwg. FP-043-2
DATA
LOW = OUTPUT ON
Dwg. WP-029-2
HIGH = ALL OUTPUTS DISABLED OUTPUT ENABLE
50%
t PLH t PHL
90%
tf DATA
tr
OUT N
10%
Dwg. WP-030-2
A. Data Active Time Before Clock Pulse (Data Set-Up Time), tsu(D) .......................................... 20 ns B. Data Active Time After Clock Pulse (Data Hold Time), th(D) .............................................. 20 ns C. Clock Pulse Width, tw(CLK) ............................................. 40 ns D. Time Between Clock Activation and Strobe, tsu(ST) ....................................................... 50 ns E. Strobe Pulse Width, tw(ST) .............................................. 50 ns F. Output Enable Pulse Width, tw(OE) ................................ 4.5 s NOTE - Timing is representative of a 12.5 MHz clock. Higher speeds are attainable.
Serial data present at the input is transferred to the shift register on the rising edge of the CLOCK input pulse. On succeeding CLOCK pulses, the registers shift data information towards the SERIAL DATA OUTPUT. Information present at any register is transferred to the respective latch on the rising edge of the STROBE input pulse (serial-to-parallel conversion). When the OUTPUT ENABLE input is high, the output source drivers are disabled (OFF). The information stored in the latches is not affected by the OUTPUT ENABLE input. With the OUTPUT ENABLE input low, the outputs are controlled by the state of their respective latches.
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6A595 8-BIT SERIAL-INPUT, DMOS POWER DRIVER
TEST CIRCUITS
INPUT
+15 V
0.11
tav IAS = 1.0 A IO DUT
OUT
VO
V(BR)DSX
VO(ON)
Dwg. EP-066-1
EAS = IAS x V(BR)DSX x tAV/2 Single-Pulse Avalanche Energy Test Circuit and Waveforms
115 Northeast Cutoff, Box 15036 Worcester, Massachusetts 01615-0036 (508) 853-5000
100 mH
6A595 8-BIT SERIAL-INPUT, DMOS POWER DRIVER
TERMINAL DESCRIPTIONS
A6A595KA A6A595KLB (DIP) (SOIC) Terminal No. Terminal No. 1-2 3 4 5-6 7 8 9-12 13 14 15-16 17 18 19-20 1-2 3 4 5-8 9 10 11-14 15 16 17-20 21 22 23-24
Terminal Name OUT2-3
Function Current-sinking, open-drain DMOS output terminals.
REGISTER CLEAR When (active) low, the registers are cleared (set low). OUTPUT ENABLE When (active) low, the output drivers are enabled; when high, all output drivers are turned OFF (blanked). POWER GROUND Reference terminal for output voltage measurements. STROBE CLOCK OUT4-7 Data strobe input terminal; shift register data is latched on rising edge. Clock input terminal for data shift on rising edge. Current-sinking, open-drain DMOS output terminals.
SERIAL DATA OUT CMOS serial-data output to the following shift register. LOGIC GROUND Reference terminal for input voltage measurements. POWER GROUND Reference terminal for output voltage measurements. LOGIC SUPPLY OUT0-1 (VDD) The logic supply voltage (typically 5 V). Current-sinking, open-drain DMOS output terminals. SERIAL DATA IN Serial-data input to the shift-register.
NOTE --Power grounds must be connected together externally.
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6A595 8-BIT SERIAL-INPUT, DMOS POWER DRIVER
A6A595KA
Dimensions in Inches (controlling dimensions)
20
11
0.014 0.008
0.430 0.280 0.240
MAX
0.300
BSC
1
0.070 0.045
0.100 1.060 0.980
BSC
10
0.005
MIN
0.210
MAX
0.015
MIN
0.150 0.115 0.022 0.014
Dwg. MA-001-20 in
Dimensions in Millimeters (for reference only)
20
11
0.355 0.204
10.92 7.11 6.10
MAX
7.62
BSC
1
1.77 1.15
2.54 26.92 24.89
BSC
10
0.13
MIN
5.33
MAX
0.39
MIN
3.81 2.93 0.558 0.356
Dwg. MA-001-20 mm
NOTES:1. Exact body and lead configuration at vendor's option within limits shown. 2. Lead spacing tolerance is non-cumulative 3. Lead thickness is measured at seating plane or below.
115 Northeast Cutoff, Box 15036 Worcester, Massachusetts 01615-0036 (508) 853-5000
6A595 8-BIT SERIAL-INPUT, DMOS POWER DRIVER
A6A595KLB
Dimensions in Inches (for reference only)
24 13
0.0125 0.0091
0.2992 0.2914
0.491 0.394 0.050 0.016
0.020 0.013
1
2
3
0.6141 0.5985
0.050
BSC NOTE 1 NOTE 3
0 TO 8
0.0926 0.1043 0.0040 MIN.
Dwg. MA-008-25 in
Dimensions in Millimeters (controlling dimensions)
24 13
0.32 0.23
7.60 7.40
10.65 10.00 1.27 0.40
0.51 0.33
1
2
3
15.60 15.20
1.27
BSC NOTE 1 NOTE 3
0 TO 8
2.65 2.35 0.10 MIN.
Dwg. MA-008-25A mm
NOTES: 1. Webbed lead frame. Leads 6, 7, 18, and 19 are internally one piece. 2. Lead spacing tolerance is non-cumulative. 3. Exact body and lead configuration at vendor's option within limits shown.
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6A595 8-BIT SERIAL-INPUT, DMOS POWER DRIVER
The products described here are manufactured under one or more U.S. patents or U.S. patents pending. Allegro MicroSystems, Inc. reserves the right to make, from time to time, such departures from the detail specifications as may be required to permit improvements in the performance, reliability, or manufacturability of its products. Before placing an order, the user is cautioned to verify that the information being relied upon is current. Allegro products are not authorized for use as critical components in life-support devices or systems without express written approval. The information included herein is believed to be accurate and reliable. However, Allegro MicroSystems, Inc. assumes no responsibility for its use; nor for any infringement of patents or other rights of third parties which may result from its use.
115 Northeast Cutoff, Box 15036 Worcester, Massachusetts 01615-0036 (508) 853-5000

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